240514_ LED_TOGGLE, COUNTER

 

무어 VS 밀리의 큰 차이 :

INPUT으로 현재상태값 + 입력 이 들어오냐  : 밀리

입력에 의해서만 정의 : 무어

 

 

`timescale 1ns / 1ps


module led_on(
   input clk,
   input reset,
   input button,
   output reg led
    );

    parameter LED_OFF = 1'b0, LED_ON = 1'b1;

    reg state, state_next;

    //state register

    always @(posedge clk, posedge reset) begin
        if(reset)begin
            state <=LED_OFF;
        end
        else begin
            state <= state_next;
        end
    end

    // Next state combinational Logic Circuit
    always @(state, button) begin
        state_next = state;
        case(state)
        LED_OFF : begin
            if(button ==1'b1) state_next = LED_ON;
            else state_next = state;
        end

        LED_ON : begin
            if(button ==1'b1) state_next = LED_OFF;
            else state_next = state;
        end

        endcase

    end

    // Output combinational Logic Circuit
    // Moore Machine
    always @(state) begin
        led = 1'b0;
        case(state)
        LED_OFF : led = 1'b0;
        LED_ON : led = 1'b1;
        endcase

    end

    // Mealy Machine
    always @(state, button) begin
        led = 1'b0;
        case(state)
        LED_OFF : begin
            if (button == 1'b1) led = 1'b1;
            else led = 1'b0;
        end 
        LED_ON : begin
            if (button == 1'b1) led = 1'b0;
            else led = 1'b1;
        end
        endcase

    end

endmodule

 

`timescale 1ns / 1ps

module button(
    input clk,
    input in,
    output out
    );

    localparam N = 3;
    reg [N-1 : 0] q_reg, q_next;
    
    always @(posedge clk) begin
        q_reg <= q_next;       
    end

    // next state logic
    always @(q_reg, in) begin
        q_next = {in, q_reg[N-1:1]};
    end

    //output logic
    assign out = (&q_reg[N-1:1] & ~q_reg[0]);
endmodule

`timescale 1ns / 1ps


module tb_button();

    
    reg clk;
    reg in;
    wire out;


    button dut(
    .clk(clk),
    .in(in),
    .out(out)
    );

    always #5 clk = ~clk;

    initial begin    
        clk = 1'b0;
        in = 1'b0;
    end

    initial begin
        #60 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #60 in = 1'b1;
        #60 in = 1'b1;
        #10 in = 1'b0;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;
        #2 in = 1'b0;
        #2 in = 1'b1;       
    end


endmodule