Always if2_ CPU_overheated

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived) 
           keep_driving = ~gas_tank_empty;


        else if(arrived)begin
            keep_driving = gas_tank_empty; 
            if((gas_tank_empty == 1)|| (cpu_overheated==1)) keep_driving = 0;
        end     
    end
    

endmodule

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived) 
           keep_driving = ~gas_tank_empty;


        else if(arrived)begin
            keep_driving = gas_tank_empty; 
            if((gas_tank_empty == 1)&& (cpu_overheated==1)) keep_driving = 0;
        end     
    end
    

endmodule

https://hdlbits.01xz.net/wiki/Always_if2

Always if2 - HDLBits