공부방/Verilog_vivado

코드를 짜는 방식

맘스터치보단파파이스 2024. 5. 8. 18:09
  • Dataflow level
  • Gate level
  • Behavioral level
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 

    always @(*)begin
        if ((sel_b1 ==1) & (sel_b2 == 1))begin
            out_always = b;
        end
        else begin
            out_always = a;
        end
    end

    assign out_assign = ((sel_b1 ==1) & (sel_b2 == 1))? b : a ;

endmodule

 

1. Dataflow level

assign문을 이용한 continuous assignment

 

2. Gate level

Gate이용

 

3. Behavioral level

always문 사용